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NCV8855 Quad-Output Automotive System Power Supply IC with Integrated High-Side 2A Switch
The NCV8855 is a multiple output controller / regulator IC with an integrated high-side load switch. The NCV8855 addresses automotive radio system and instrument cluster power supply requirements. In addition to the high-side load switch, the NCV8855 includes a switch-mode power supply (SMPS) buck controller, a 2.5 A SMPS buck regulator and two low dropout (LDO) linear regulator controllers. The NCV8855 in combination with the ultra-low quiescent current NCV861x IC forms an eight-output automotive radio or instrument cluster power solution. The NCV8855 has an internally set switching frequency of 170 kHz, with a SYNC pin for external frequency synchronization. The NCV8855 is intended to supply power to various loads, such as a tuner, CD logic, audio processor and CD / tape control within a car radio. The high-side switch can be used for a CD / tape mechanism or switching an electrically-powered antenna or display unit. In an instrument cluster application, the NCV8855 can be used to power graphics display, flash memory and CAN transceivers. In addition, the high-side switch can be used to limit power to a TFT display during a battery over-voltage condition.
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1 40 40 PIN QFN, 6x6 MN SUFFIX CASE 488AR A WL YY WW G
NCV8855 AWLYYWWG
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
ORDERING INFORMATION
Device Package Shipping 2500 / Tape & Reel
* * * * * * * * * * * * * *
< 1 mA Shutdown Current Meets ES-XW7T-1A278-AB Test Pulse G - Loaded Conditions VIN Operating Range 9.0 to 18.0 V 1 SMPS Controller with Adjustable Current Limit 1 SMPS Regulator with Internal 300 mW NMOS Switch 2 LDO Controllers with Current Limit and Short Circuit Protection 1 High-side Load Switch with Internal 300 mW NMOS FET Adjustable Output Voltage for All Controllers / Regulators 800 mV, $1% Reference Voltage System Enable Pin Single Enable Pin for Both LDO Controllers Independent Enable for High-side Load Switch Thermal Shutdown with Thermal Warning Indicator This is a Pb-Free Device
NCV8855BMNR2G QFN-40 (Pb-Free)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
Applications
* Automotive Radio * Instrument Cluster, Driver Information System (DIS)
(c) Semiconductor Components Industries, LLC, 2010
May, 2010 - Rev. 1
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Publication Order Number: NCV8855/D
NCV8855
TYPICAL APPLICATION SCHEMATIC SHOWING DETAILED BLOCK DIAGRAM
DRV_VPP SYS _EN
22 5
VIN Bandgap V1 VR
DRV_VPP ILIMIT
VIN
5V_IC I LIMIT
35
5V_IC
V1 VR VIN LDO
36 11
DRAIL BST2 VIN_SW VBATT
VBATT
BST1 Q1 GH1 SN1 Q2 GL1
25 Gate Control 24 23 21 QS QR CLK1 CLK2 SQ R ILIMIT V REF
10
VOUT1
9 SS2
SN2 D1
VOUT2
OCSET
ILIMIT 27 SS1 V REF EA RAMP1 70% VREF SCP SCP RAMP2 EA
3 2
SW_FB2 COMP2 SYNC
SW_FB1 COMP1
29 30 DRV_VPP 5V_IC UVLO
CLK1 RAMP1 CLK2 RAMP2
OSC 180 out-of-phase 4
HOT_FLG
8
TWARN1 TWARN2
Main Logic / Fault Control TSD1 TSD2 Int. rails and references V REF 5V_IC ILIMIT
7 6
HS_EN LDO_EN
VOUT1
ISNS1+ ISNS1-
40 39 1 38 ILIMIT
31 32
ISNS2+ ISNS2- LR _G2 LR_FB2 Q4
VBATT
VOUT3
Q3
LR_G1 LR_FB1
VREF EA
EA
33 34
VOUT4
SCP 70% VREF VBATT VIN 26 VIN
SCP 70% VREF Control CLK1
HS_OUT
HS_S
28
Current Limit
Vneg clamp
Vhigh clamp
Charge Pump
37 AGND
20 PGND
Figure 1. Application Schematic / Block Diagram
Components D1 Q1, Q2 Q3, Q4
Part Number MBRS4201T3 NTD24N06 NTD20P06LT4G
Value 200 V, 4 A, Schottky, 0.61 V Vf, SMC 60 V, N type MOSFET, 32 mW , DPAK -60V, P type MOSFET, 130 mW, DPAK
Manufacturer ON Semiconductor ON Semiconductor ON Semiconductor
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NCV8855
PIN FUNCTION DESCRIPTIONS
Pin No. 5 6 7 8 22 35 36 4 37 Symbol SYS_EN LDO_EN HS_EN HOT_FLG DRV_VPP 5V_IC DRAIL SYNC AGND Description Main enable pin for the IC. A logic high on this pin will enable the part. Leaving this pin floating or driving it to ground will place the IC in shutdown mode. Enable pin for both LDO controllers. A logic high on this pin will enable both LDO controllers. If this pin is left floating, an internal pull down keeps the LDOs disabled. Enable pin for the high-side load switch. A logic high on this pin will enable the HSS. If this pin is left floating, an internal pull down keeps the HSS disabled. Thermal warning indicator. This pin provides an early warning signal of an impending thermal shutdown. Output of the internal 7.2 V linear regulator. Bypass this pin with 1 mF to ground. Output of the internal 5 V linear regulator. Bypass this pin with 0.1 mF to ground. Output of the internal 4.2 V linear regulator. Bypass this pin with 0.1 mF to ground. Synchronization pin. Use this pin to synchronize the internal oscillator to an external clock. If synchronization is not used, connect this pin to AGND. Analog ground. Reference point for internal signals.
SWITCH-MODE POWER SUPPLY 1 (SMPS1) PIN CONNECTIONS 27 29 30 OCSET SW_FB1 COMP1 Overcurrent set pin, used to set the current limit threshold. A resistor connected from this pin and the upper MOSFET Drain sets the current limit protection level. Output voltage feedback pin. Connect a resistor divider network to VOUT1 to set the desired output voltage.
This pin is the output of the error amplifier and the non-inverting input of the PWM comparator. Use this pin in conjunction with the SW_FB1 pin to compensate the voltage-mode control feedback loop.
This pin is the supply rail for the upper N-Channel MOSFET. An internal bootstrap diode brings DRV_VPP to this pin. Connect a ceramic capacitor (CBST1) between this pin and the SN1 pin. A typical value for CBST1 is 0.1 mF. GH1 is the output pin of the internal upper N-Channel MOSFET gate driver. Keep the trace from this pin to the gate of the upper MOSFET as short as possible to achieve the best turn-on and turn-off performance and to reduce electro-magnetic emissions. This pin is the return path of the upper floating gate driver. Connect this pin to the source of the upper MOSFET. This pin is also used to sense the current flowing through the upper MOSFETs. GL1 is the output pin of the synchronous rectifier gate driver. Connect this pin to the lower N-channel MOSFET. This pin is the return path for SMPS1 lower MOSFET driver current. Connect this pin to the source of the lower MOSFET.
25
BST1
24
GH1
23 21 20
SN1 GL1 PGND
PINS NOT INTERNALLY CONNECTED TO SILICON EP 12 thru 19 - Exposed pad of QFN package. Connect to printed circuit board ground to improve thermal performance. These pins can be left floating or tied to ground to improve thermal performance.
SWITCH-MODE POWER SUPPLY 2 (SMPS2) PIN CONNECTIONS 10 VIN_SW This pin is the supply rail for the internal upper N-Channel MOSFET. Bypass this pin with a local ceramic capacitor. Additional bulk capacitance may be required based off output requirements. Refer to application section for more information. Output voltage feedback pin. Connect a resistor divider network to VOUT2 to set the desired output voltage. This pin is the output of the error amplifier and the non-inverting input of the PWM comparator. Use this pin in conjunction with the SW_FB2 pin to compensate the voltage-controlled feedback loop. This pin is the supply rail for the internal upper N-Channel MOSFET. An internal bootstrap diode brings DRV_VPP to this pin. Connect a ceramic capacitor (CBST2) between this pin and the SN2 pin. A typical value for CBST2 is 0.1 mF. Source output of the internal upper N-channel MOSFET.
3 2 11
SW_FB2 COMP2 BST2
9
SN2
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NCV8855
PIN FUNCTION DESCRIPTIONS
Pin No. Symbol Description LOW DROPOUT LINEAR REGULATOR CONTROLLER 1 (LDO1) PIN CONNECTIONS 38 1 40 LR_FB1 LR_G1 ISNS1+ LDO controller output voltage feedback pin. Connect a resistor divider network to VOUT3 to set the desired output voltage. Error amplifier output of the LDO controller. Connect to gate of P-Channel MOSFET pass element. Current sense positive input. Connect this pin to the supply side of the current sense resistor. This pin also serves as the supply rail for the linear regulator controller. A local bypass capacitor with a value of 0.1 mF to 1 mF is recommended. Current sense negative input. When using a current sense resistor, connect this pin to the pass element side of the current sense resistor. If current limit is not used, connect this pin to the supply rail of the pass element.
39
ISNS1-
LOW DROPOUT LINEAR REGULATOR CONTROLLER 2 (LDO2) PIN CONNECTIONS 34 33 31 LR_FB2 LR_G2 ISNS2+ LDO controller output voltage feedback pin. Connect a resistor divider network to VOUT3 to set the desired output voltage. Error amplifier output of the LDO controller. Connect to gate of P-Channel MOSFET pass element. Current sense positive input. Connect this pin to the supply side of the current sense resistor. This pin also serves as the supply rail for the linear regulator controller. A local bypass capacitor with a value of 0.1 mF to 1 mF is recommended. Current sense negative input. When using a current sense resistor, connect this pin to the pass element side of the current sense resistor. If current limit is not used, connect this pin to the supply rail of the pass element.
32
ISNS2-
HIGH-SIDE LOAD SWITCH (HSS) PIN CONNECTIONS 26 28 VIN HS_S This pin is the supply rail for the internal high-side load switch, DRV_VPP and 5V_IC. Bypass this pin with a 1 mF ceramic capacitor. Source node output of the internal high-side N-Channel MOSFET load switch.
MAXIMUM RATINGS (Voltages are with respect to AGND unless noted otherwise)
Pin Name Max dc voltage (GH1, BST1, SN1, SN2, BST2, HS_S) Negative Transient (t < 50 ns) (SN1, SN2) Max dc voltage: 5V_IC Max dc voltage: DRV_VPP Max dc voltage (BST1 & GH1w/respect to SN1, GL1, BST2 w/respect to SN2) Max dc voltage (OCSET, ISNS1+, ISNS1-, LR_G1, VIN, VIN_SW, ISNS2+, ISNS2-, LR_G2) Peak Transient (ES-XW7T-1A278-AB Test Pulse G - Loaded Conditions) (OCSET, ISNS1+, ISNS1-, LR_G1, VIN, VIN_SW, ISNS2+, ISNS2-, LR_G2) Max dc voltage (SW_FB1, COMP1, LR_FB1, LDO_EN, HOT_FLG, SW_FB2, COMP2, LR_FB2, HS_EN, SYS_EN, SYNC) Max dc voltage: PGND Maximum Operating Junction Temperature Range, TJ Maximum Storage Temperature Range, TSTG Peak Reflow Soldering Temperature: Pb-Free 60 to 150 seconds at 217C Value -0.3 to 30 -2 6 9 -0.3 to 15 -0.3 to 40 -0.3 to 45 -0.3 to 7 -0.3 to 0.3 -40 to 150 -55 to +150 260 peak Unit V V V V V V V V V C C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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NCV8855
ATTRIBUTES
Description Thermal Characteristic RqJA generated from 1 sq in / 1 oz copper 1 sided PCB ESD Capability Human Body Model (SN1, SN2) Human Body Model (All Others) Machine Model Moisture Sensitivity Level MSL Symbol RqJA RqJC Value 36 3 1 2 150 1 Unit C/W C/W kV kV V
RECOMMENDED OPERATING CONDITIONS
Description VBATT range (refer to Figure 1) Ambient Temperature range
ISNS1+ 1 ISNS2+ LR_FB1 LR_FB2
Value 9 V to 18 V -40C to 105C
ISNS2-
ISNS1-
LR_G2
DRAIL
AGND
5V_IC
LR_G1 COMP2 SW_FB2 SYNC/ROSC SYS_EN
COMP1 SW_FB1 HS_S OCSET VIN Top View BST1 GH1 SN1 DRV_VPP GL1
LDO_EN HS_EN HOT_FLG SN2 VIN_SW
ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1- = VISNS2+ = VISNS2- = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range -40C v TJ v 150C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation.
Parameter Symbol Conditions Min Typ Max Unit
SUPPLY VOLTAGES AND SYSTEM SPECIFICATION
Supply Current and Operating Voltage Range VIN_SW quiescent current VIN_SW shutdown current High VIN detect voltage High VIN detect hysteresis VIN quiescent current VIN shutdown current VOVP No Switching, VSW_FB2 = 1V, SN2 = PGND1, TJ = 25C SYS_EN = 0 V, TJ = 25C VIN rising VIN falling TJ = 25C SYS_EN = 0 V, TJ = 25C 18 0.2 175 100 18.5 0.6 4 100 500 500 19 1 mA nA mA nA V
1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters.
BST2
PGND
Figure 2.
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NCV8855
ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1- = VISNS2+ = VISNS2- = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range -40C v TJ v 150C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation.
Parameter Symbol Conditions Min Typ Max Unit
SUPPLY VOLTAGES AND SYSTEM SPECIFICATION
Internal Voltage Reference Internal voltage reference range Internal Linear Regulator 5 V Supply Rail 5V_IC UVLO threshold voltage 5V_IC UVLO hysteresis Voltage range Current limit Load regulation Line regulation Internal DRV_VPP Supply Rail DRV_VPP UVLO threshold voltage DRV_VPP UVLO hysteresis Voltage range Current limit Load regulation Line regulation Dropout voltage Oscillator Oscillator frequency SYNC Logic high Logic low Pull down current Leakage current Clock synchronization range Synchronization delay to SMPS1 Synchronization delay to SMPS2 Minimum SYNC pulse width (HIGH) Minimum SYNC pulse width (LOW) From falling SYNC edge From rising SYNC edge SMPS1 synchronizing SMPS2 synchronizing VSYNC = 5 V VSYNC = 0.8 V SYS_EN = 0 V, VSYNC = 5 V 190 200 200 0.8 2 5 5 100 10 500 255 400 400 50 50 2.0 V V mA nA kHz ns ns ns ns fSW 154.7 170 185.3 kHz 1 mA v IDRV_VPP v 25 mA IDRV_VPP = 1 mA, 9 V v VIN v 18 V IDRV_VPP = 25 mA, DVDRV_VPP = 2 % VDRV_VPP VDRV_VPP rising VDRV_VPP falling No load 4.00 100 6.9 30 4.35 150 7.1 67 4.70 300 7.3 110 50 200 400 V mV V mA mV mV mV 1mA v I5V_IC v 10 mA I5V_IC = 5 mA, 9 V v VIN v 18 V V5V_IC rising V5V_IC falling No load 4.00 100 4.8 10 4.35 150 5 21 4.70 300 5.2 50 50 100 V mV V mA mV mV VREF TJ = 25C -40C v TJ v 150C 0.792 0.784 0.8 0.808 0.816 V
Thermal Monitoring (TMON_HSS, High-side junction temperature monitor) Thermal warning temperature TWARN1 hysteresis Thermal shutdown temperature Delta junction temperature (TSD1-TWARN1) Thermal Monitoring (TMON_SW, SMPS2 internal MOSFET temperature monitor) Thermal warning temperature TWARN2 140 150 160 C 1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters. TSD1 TWARN1 140 10 160 10 170 20 150 160 20 180 30 C C C C
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NCV8855
ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1- = VISNS2+ = VISNS2- = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range -40C v TJ v 150C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation.
Parameter Symbol Conditions Min Typ Max Unit
SUPPLY VOLTAGES AND SYSTEM SPECIFICATION
Thermal Monitoring (TMON_SW, SMPS2 internal MOSFET temperature monitor) TWARN2 hysteresis Thermal shutdown temperature Delta junction temperature (TSD2-TWARN2) HOT_FLG Voltage low threshold Leakage current Sink capability System Enable Logic high Logic low Pull down resistance High-Side Enable HS_EN logic high HS_EN logic low Pull down current Leakage current LDO Enable Logic high Logic low Pull down current Leakage current ILDO_EN VLDO_EN = 5 V VLDO_EN = 0.8 V SYS_EN = 0 V, VLDO_EN = 5 V 0.8 2 5 5 100 10 500 2.0 V V mA nA IHS_EN VHS_EN = 5 V VHS_EN = 0.8 V SYS_EN = 0 V, VHS_EN = 5 V 0.8 2 5 5 100 10 500 2.0 V V mA nA TJ = 25C 500 2.0 0.8 V V kW TJ > TWARN[x], 1 kW pullup to 5 V 1 kW pull-up to 5 V, TJ = 25C VHOT_FLG = 0.8 V 4.6 100 0.4 500 V nA mA TSD2 10 160 10 170 20 20 180 30 C C C
SWITCH-MODE POWER SUPPLY CONTROLLER (SMPS1, VOUT1) SPECIFICATIONS
Over Current Protection OCSET current sink OCSET leakage current OCSET comparator differential range OCSET comparator common-mode range Current limit response time Short circuit threshold voltage Short circuit protection startup delay Internal Soft-Start Soft-start time tSS1 3 5 7 ms SCTH1 ROCSET = 10 kW connected to 13.2 V SYS_EN = 0 V, VOCSET = 13.2 V, TJ = 25C (Note 1) (Note 1) From rising edge of SN1 VSW_FB1 % of VREF From SYS_EN rising edge, % of tSS1, SW_FB1 = 0.5 V, (Note 2) 50 4.0 100 75 100 200 80 125 45 55 100 65 500 750 19 275 85 150 mA nA mV V ns % %
1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters.
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NCV8855
ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1- = VISNS2+ = VISNS2- = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range -40C v TJ v 150C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation.
Parameter Symbol Conditions Min Typ Max Unit
SWITCH-MODE POWER SUPPLY CONTROLLER (SMPS1, VOUT1) SPECIFICATIONS
Error Amplifier Dc gain Gain-bandwidth product SW_FB1 input bias current Input offset voltage Slew rate COMP1 source current (Note 1) (Note 1) SW_FB1 = 0.8 V (Note 1) CCOMP1 = 50 pF, $1 mA dc load Slew rate within ramp voltage levels (Note 1) VCOMP1 = 2.2 V VCOMP1 = 3.2 V COMP1 sink current VCOMP1 = 2.2 V VCOMP1 = 1.1 V Minimum COMP1 voltage Maximum COMP1 voltage Ramp maximum voltage Ramp minimum voltage Ramp voltage amplitude Duty Cycle Limitations Minimum off time Minimum pulse width Gate Driver GH1 source current GH1 sink current GL1 source current GL1 sink current SN1 falling to GL1 rising, non-overlap time GL1 falling to GH1 rising, non-overlap time SN1 falling non-overlap threshold voltage GL1 falling non-overlap threshold voltage SN1 falling override timer 50 1.0 tNOLT VGH1 - VSN1 = 4 V, TJ = 25C VGH1 - VSN1 = 2 V, TJ = 25C VGL1 - PGND = 4 V, TJ = 25C VGL1 - PGND = 1 V, TJ = 25C 1.5 1.5 1.5 1.5 30 30 1.8 2 100 150 70 70 3.0 A A A A ns ns V V ns tMINOFF1 tMINON1 GH1 falling to GL1 rising GH1 rising to GH1 falling 80 120 140 250 200 300 ns ns VRAMP1 ICOMP1 = 500 mA ICOMP1 = 2 mA 3.3 2.8 1.1 1.6 3.0 1.2 1.8 3.2 1.3 2.0 6 1.5 1.6 1.1 0.7 8 8 8 8 8 1.05 70 8 85 10 100 800 dB MHz nA mV V/ms mA mA mA mA V V V V V
SWITCH-MODE POWER SUPPLY REGULATOR (SMPS2, VOUT2) SPECIFICATIONS
Over Current Protection Internal current limit Current limit blanking time Short circuit threshold voltage Short circuit protection startup delay SCTH2 VSW_FB2 % of VREF From SYS_EN rising edge, % of tSS2, SW_FB2 = 0.5 V 2.5 100 75 100 85 125 3.05 4.2 200 95 150 A ns % %
1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters.
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NCV8855
ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1- = VISNS2+ = VISNS2- = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range -40C v TJ v 150C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation.
Parameter Symbol Conditions Min Typ Max Unit
SWITCH-MODE POWER SUPPLY REGULATOR (SMPS2, VOUT2) SPECIFICATIONS
Internal Soft-start Soft-start time Error Amplifier Dc gain Gain-bandwidth product SW_FB2 input bias current Input offset voltage Slew rate COMP2 source current CCOMP2 = 50 pF, 1 mA dc load Slew rate within ramp voltage levels (Note 1) VCOMP2 = 2.2 V VCOMP2 = 3.2 V COMP2 sink current VCOMP2 = 2.2 V VCOMP2 = 1.1 V Minimum COMP2 voltage Maximum COMP2 voltage Ramp maximum voltage Ramp minimum voltage Ramp voltage amplitude Duty Cycle Limitations Minimum off time Minimum pulse width Switching MOSFET N-channel MOSFET RDS(on) Turn-on time Turn-off time TJ = 25C, Guaranteed at Probe SN2 0 V to 13.2 V, IOUT = 1 A (inductive load), TJ = 25C SN2 13.2 V to 0 V, IOUT = 1 A (inductive load), TJ = 25C 300 30 30 360 mW ns ns tMINOFF2 tMINON2 SN2 falling to SN2 rising SN2 rising to SN2 falling, 80 120 140 250 200 300 ns ns VRAMP2 ICOMP2 = 500 mA ICOMP2 = 2 mA 3.3 2.8 1.1 1.6 3.0 1.2 1.8 3.2 1.3 2.0 6 1.5 1.6 1.1 0.7 8 8 8 8 8 1.05 (Note 1) (Note 1) SW_FB2 = 0.8 V 70 8 85 10 100 500 800 dB MHz nA mV V/ms mA mA mA mA V V V V V tSS2 SYNC floating 3 5 7 ms
LOW DROPOUT LINEAR REGULATOR CONTROLLER (LDO1, VOUT3) SPECIFICATIONS
Output Voltage Regulation Output voltage accuracy Output voltage line regulation Output voltage load regulation Output load capacitance range Output load capacitance ESR range Power supply ripple rejection Current Limit Current limit threshold voltage VSNS1 VISNS1+ - VISNS1- 90 110 130 mV PSRR1 COUT3 VLR_FB1 tied to VOUT3 directly, NTD20P06L pass device IOUT3 = 10 mA, 4.5 V v VISNS1+ v 5.5 V, NTD20P06L pass device 1 mA v IOUT3 v 500 mA, VISNS1+ = 5 V, NTD20P06L pass device (Note 1) (Note 1) NTD20P06L pass device (Note 1) -2 -0.25 -0.5 10 0.01 60 0.01 0.2 2 0.25 0.5 100 5 % % % mF W dB
1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters.
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NCV8855
ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1- = VISNS2+ = VISNS2- = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range -40C v TJ v 150C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation.
Parameter Symbol Conditions Min Typ Max Unit
LOW DROPOUT LINEAR REGULATOR CONTROLLER (LDO1, VOUT3) SPECIFICATIONS
Current Limit ISNS1+ leakage current ISNS1- leakage current Short circuit threshold voltage Short circuit blanking time Error Amplifier Feedback bias current Maximum |VGS| LR_FB1 = 0.5 V 2 mA, internally clamped 10 100 11.7 500 13.5 nA V IISNS1+ IISNS1- SYS_EN = 0, TJ = 25C, VISNS1+ = 13.2 V SYS_EN = 0, TJ = 25C, VISNS1- = 13.2 V VLR_FB1 % of VREF From rising edge of LDO_EN 60 10 100 100 70 12 500 500 80 14 nA nA % ms
LOW DROPOUT LINEAR REGULATOR CONTROLLER (LDO2, VOUT4) SPECIFICATIONS
Output Voltage Regulation Output voltage accuracy Output voltage line regulation Output voltage load regulation Output load capacitance range Output load capacitance ESR range Power supply ripple rejection Current Limit Current limit threshold voltage ISNS2+ leakage current ISNS2- leakage current Short circuit threshold voltage Short circuit blanking time Error Amplifier Feedback bias current Maximum |VGS| LR_FB2 = 0.5 V 2 mA, internally clamped 10 100 11.7 500 13.5 nA V VSNS2 IISNS2+ IISNS2- VISNS2+ - VISNS2- SYS_EN = 0, TJ = 25C, VISNS2+ = 13.2 V SYS_EN = 0, TJ = 25C, VISNS2- = 13.2 V VLR_FB2 % of VREF From rising edge of LDO_EN 60 10 90 110 100 100 70 12 130 500 500 80 14 mV nA nA % ms PSRR2 COUT4 VLR_FB2 tied to VOUT4 directly, NTD20P06L pass device IOUT4 = 10 mA, 9 V v VISNS2+ v 18 V, NTD20P06L pass device 1 mA v IOUT4 v 500 mA, NTD20P06L pass device (Note 1) (Note 1) NTD20P06L pass device (Note 1) -2 -0.25 -0.5 10 0.01 60 0.01 0.2 2 0.25 0.5 100 5 % % % mF W dB
High-side Load Switch (HSS)
Current Limit Peak current limit Short circuit timeout Short circuit threshold voltage Current overload threshold voltage Current overload timeout Voltage Clamp Source output positive clamping voltage Source output negative clamping voltage VCLAMP+ VCLAMP- 1 mA v IHS_S v 2 A VCLAMP+ v VIN v VOVP ILOADSW = 50 mA 15.4 -1.6 16.0 16.6 V V IHSSLIM tSCP VSCP(HS_S) VDS VIN - VHS_S 2.00 1.300 4.0 3.3 2.600 2.80 1.506 4.5 3.95 3.012 3.64 1.800 5.0 4.6 3.600 A ms V V ms
1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters.
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NCV8855
ELECTRICAL CHARACTERISTICS (VIN_SW = VIN = VISNS1+ = VISNS1- = VISNS2+ = VISNS2- = 13.2 V, SYS_EN = LDO_EN = HS_EN = 5 V, VOUT3 = 3.3 V, VOUT4 = 8.5 V, IOUT[1:4] = 0 A) Min/Max values are valid for the temperature range -40C v TJ v 150C unless noted otherwise. Min/Max values are guaranteed by test, design or statistical correlation.
Parameter Symbol Conditions Min Typ Max Unit
High-side Load Switch (HSS)
MOSFET HSS RDS(on) HSS dropout voltage Turn On/Off Turn on time (resistive load) Turn off time RHS_S = 6.6 W, 90% VIN RHS_S = 6.6 W, 10% VIN 40 50 80 125 120 200 ms ms VGS(HSS) = 8 V IHS_S = 1 A 233 233 442 442 mW mV
1. Guaranteed by design, not fully tested in production. 2. Indirectly guaranteed by test coverage of other parameters.
1.506 msec
3.012 msec
VDS w 3.75 V
VHS_S
VDS=3.75V 4.5V
ILOAD
2.8A
HS_EN
HS Current Overload
(Latched shutdown of HS only)
Figure 3.
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NCV8855
TYPICAL PERFORMANCE CHARACTERISTICS
169.4 169.2 169.0 168.8 fSW (kHz) 168.4 168.2 167.8 167.6 167.4 -50 -25 0 25 50 75 100 125 150 0.796 -50 -25 0 25 50 75 100 125 150 168.0 0.798 VREF (V) 168.6 0.802 0.800 0.804 0.808
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 4. Switching Frequency vs. Junction Temperature
3.2 3.1 HSS CURRENT LIMIT (A) 3.0 tNOL (ns) 2.9 2.8 2.7 2.6 2.5 2.4 -50 -25 0 25 50 75 100 125 150 65 60 55 50 45 40 35 30 -50
Figure 5. Reference Voltage vs. Junction Temperature
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 6. HSS Current Limit vs. Junction Temperature
7.18 7.16 VDRV_VPP (V) 7.14 7.12 7.10 7.08 7.06 -50 80.8 80.6 80.4 80.2 SCTH (%) 80.0 79.8 79.6 79.4 79.2 79.0 78.8 -25 0 25 50 75 100 125 150 78.6 -50
Figure 7. SMPS1 Non-Overlap Time vs. Junction Temperature
SMPS2
SMPS1
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 8. Drive Voltage vs. Junction Temperature
Figure 9. Short Circuit Threshold vs. Junction Temperature
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NCV8855
TYPICAL PERFORMANCE CHARACTERISTICS
1.820 1.815 1.810 tMINON (ns) VRAMP (V) 1.805 SMPS1 SMPS2 220 215 210 205 200 195 190 -25 0 25 50 75 100 125 150 185 -50 -25 0 25 50 75 100 125 150
1.800 1.795 1.790 1.785 -50
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 10. Ramp Amplitude vs. Junction Temperature
0.14 0.12 IOCSET_L, (mA) 0.10 0.08 0.06 0.04 0.02 0.00 -50 -25 0 25 50 75 100 125 150 IOCSET, (mA) 56.6 56.4 56.2 56.0 55.8 55.6 55.4 55.2 55.0 -50
Figure 11. Minimum On Time vs. Junction Temperature
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 12. OCSET Leakage Current vs. Junction Temperature
2.5 2.0 IHS_EN, (mA) 1.5 1.0 0.5 0.0 -50 109.5 109.0 108.5
Figure 13. OCSET Current Sink vs. Junction Temperature
VSNS (mV)
108.0 LDO1 107.5 107.0 106.5 -50 LDO2 -25 0 25 50 75 100 125 150
-25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 14. HS EN Leakage Current vs. Junction Temperature
Figure 15. LDO Current Limit vs. Junction Temperature
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NCV8855
TYPICAL PERFORMANCE CHARACTERISTICS
0.18 0.16 0.14 ILDO_EN (mA) 0.12 0.10 0.08 0.06 0.04 0.02 0.00 -50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C)
Figure 16. LDO EN Leakage Current vs. Junction Temperature
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NCV8855
THEORY OF OPERATION
Device Description Linear Regulator Enable (LDO_EN)
The NCV8855 is a multiple output controller / regulator IC with an integrated high-side load switch. The NCV8855 will address automotive radio system and instrument cluster power supply requirements. In addition to the high-side load switch, the NCV8855 comprise a switch-mode power supply (SMPS) buck controller, a 2 A SMPS buck regulator, and two low dropout linear regulator controllers (LDO). The NCV8855 in combination with the ultra-low Iq NCV861x IC forms an eight output automotive radio or instrument cluster power solution.
DRV_VPP 5V_IC 22 35 SYS_EN 5 6 LDO_EN MAIN 8 HOT_FLG 11 BST2 10 VIN_SW 9 SN2 SMPS1 VOUT1 SMPS2 VOUT2
The low-dropout linear regulators (LDOs) have a dedicated enable pin. This pin controls the startup and shutdown of the LDOs. The SYS_EN pin must be logic high for this pin to function. It is possible to drive this pin high coincidentally with SYS_EN, but the LDO outputs will not startup until DRV_VPP and 5V_IC have increased above its UVLO thresholds.
High-Side Switch Enable (HS_EN)
The high-side switch enable controls only the high-side switch. Similar to LDO_EN, the SYS_EN pin must be logic high for this pin to function. The voltage level on all enable pins have been designed to work with 3.3 V or 5 V logic.
IC Power (VIN, VIN_SW, DRV_VPP, 5V_IC)
BST1 25 GH1 24 SN1 23 GL1 21 OCSET 27 SW_FB1 29 COMP1 30 ISNS1+ 40 ISNS1- 39 LR_G1 1 LR_FB1 38 VIN 26 HS_S 28
3 SW_FB2 2 COMP2 4 SYNC/ ROSC 31 32 33 34 ISNS2+ ISNS2- LR_G2 LR_FB2
There are many input voltage rails for the NCV8855. The main power supply input for the IC is VIN. The DRV_VPP, 5V_IC and the high-side switch drain are all driven from VIN. The DRV_VPP voltage rail is the power rail for SMPS1 & SMPS2's gate driver circuits. The 5V_IC voltage rail is the main supply for the IC. The VIN_SW rail is the supply rail for SMPS2's internal upper MOSFET. VIN_SW is directly tied to the drain of the N-channel MOSFET.
SMPS2 Internal upper MOSFET
LDO2 VOUT4
LDO1 VOUT3
High-Side Switch VIN DRV_VPP internal DRV_VPP regulator
VIN_SW
HIGH-SIDE SWITCH 37 20
7 HS_EN
5V_IC internal regulator 5V_IC
AGND PGND
Figure 17.
SMPS1 & 2 Gate Drivers
Main IC
The NCV8855 has an internally set switching frequency of 170 kHz and provides an SYNC pin for external frequency synchronization. The NCV8855 is designed to operate within the range of 9 V to 18 V. The switch-mode power supplies are voltage-mode controlled and the LDO controllers drive P-channel MOSFETs as pass devices.
System Enable (SYS_EN)
ISNS1+ LDO1 ISNS1- LDO2
ISNS2+
ISNS2-
Figure 18.
The system enable (SYS_EN) pin is used to start device operation or place it in low quiescent shutdown. Driving this pin high will allow the two main internal voltage rails (DRV_VPP and 5V_IC) to power up. These voltage rails require external bypassing and have independent UVLO trip points. Both rails must be operational in order for the IC to function. After exceeding its UVLO threshold, the IC will power up the switch-mode power supplies with a soft-start. Conversely, a logic-low on the pin will power down the DRV_VPP and 5V_IC rails and place the IC in an ultra-low current shutdown state.
Two additional inputs rails are ISNS1+ and ISNS2+. These inputs not only serve as the positive reference for the current sense circuit, but also serve as the supply rail for the LDO error amplifier.
Startup and Shutdown Behavior
The startup sequence primary depends on the system configuration. However, in every case, enable SYS_EN first. The SYNC pin must not be held at logic high before SYS_EN is enabled. Below shows typical startup and
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NCV8855
shutdown behavior when VOUT3 is derived from VOUT1 (as shown in Figure 1).
Startup and Shutdown Behavior
18.5 V 17.9 V
re-start the high-side switch in the case of a TMON_HSS TSD event. If thermal monitor 2 (TMON_SW) exceeds it TSD point, the entire chip (regardless of the state of TMON_HSS) will latch off, and a SYS_EN toggle will be required to restart.
Overcurrent Protection (SMPS1)
VIN SYS_EN 8V_IC 5V_IC VOUT1 VOUT2 LDO_EN VOUT3 VOUT4 Natural Startup Natural Decay Controlled Soft-Star
>2.2 V <0.8 V >2.2 V <0.8 V 4.35 V 4.2 V 4.35 V 4.2 V
Overcurrent protection for SMPS1 is implemented via VDS(on) sensing of the upper MOSFET. At the beginning of each switching cycle, after a short blanking time, the voltage is sampled across the upper MOSFET and compared to the threshold set by ROCSET.
OCSET 27 External upper MOSFET ILIMIT 23 SN1 50 A ROCSET
Figure 19.
In addition to the enable pins, the IC features an automatic shutdown during a high battery condition. When VIN exceeds 18.5 V (typ) the IC will shutdown all outputs. When VIN falls below 17.9 V (typ), the IC will go through a typical start up and resume normal operation.
Out-of-Phase Synchronization
Figure 20.
By default, the turn-on of SMPS2 is delayed by half the switching cycle, which corresponds to 180 phase delay. Advantages of out-of-phase synchronization are many. Interleaving the current pulses at the input reduces the input RMS current. This reduction minimizes the input filter requirement, allowing the use of smaller components, hence a more cost effective solution. In addition, since peak current is reduced, emitted EMI is also reduced.
Synchronizing (SYNC)
If this comparator is tripped, then the pulse is immediately halted. This operation repeats every cycle until the overcurrent condition is removed. The over-current limit can be calculated with the following equation:
I LIMIT + R OCSET I OCSET R DS(on)
(eq. 1)
Synchronizing the NCV8855 to an external frequency is achieved by providing a 10 to 90% duty cycle clock to the SNYC pin. The rising edge of the clock signal will immediately reset the internal RAMP of SMPS2 and begin a new pulse for SMPS2. Conversely, the falling edge of the clock signal will immediately reset the internal RAMP of SMPS1 and begin a new pulse for SMPS1. The first rising edge of the external clock signal may cause a momentary phase diversion between SMPS1 and SMPS2, but will lock into desired phase on the subsequent falling edge. During start up, the SYNC pin must not be held at a logic high.
Thermal Warning (HOT_FLG) and Thermal Shutdown
where, IOCSET is 50 mA (typ.). To calculate the ROCSET value, the maximum RDS(on) (at temperature) and the minimum value of IOCSET must be used. In addition to this, the following relationship should be met:
I LIMIT w IOUT1 MAX ) I pk-pk 2
(eq. 2)
There are two thermal sensors in the NCV8855 devices. If any of these two exceeds the warning threshold, the HOT_FLG will assert low. In addition, if thermal monitor 1 (TMON_HSS) exceeds the warning threshold, the high-side switch current limit will fold back to 1.4 A (typ). If TMON_HSS exceeds its TSD point, the high-side switch will latch off while the other device functions will continue to operate. A HS_EN or SYS_EN toggle will be required to
where IOUT1(MAX) is the maximum dc current allowed, and Ipk-pk/2 is the peak ripple current above the dc value. This will insure that undesirable trigger of the over-current protection is avoided. To protect in the case of a short circuit event, a comparator monitoring the feedback voltage is incorporated. If the output voltage goes below 70% of nominal after start-up, the part is latched off, requiring SYS_EN to be toggled to restart the part. The over current protection circuitry is active upon startup (short circuit protection is not). During soft-start, under normal conditions, the current limit circuit should not trip. However, with large output capacitance, the current limit circuit may determine the output voltage rise time instead of the soft-start circuit. To ensure that the output voltage is
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NCV8855
controlled by the soft-start circuit make dtlimit v TSS1, where TSS1 is the soft-start time and dtlimit is equal to:
COUT1 * VOUT1 I LIMIT Overcurrent Protection (SMPS2)
(eq. 3)
The current limit for SMPS2 is internally set at 3.05 A (typ). The operation is similar to SMPS1 in that it immediately ends the pulse upon overcurrent detection. This repeats every cycle until the overcurrent condition is removed. Similar to SMPS1, the over current protection circuitry is active upon startup. As with SMPS1, short circuit protection is implemented with a comparator monitoring the feedback. If the output voltage goes below 70% of nominal after start-up, the part is latched off, requiring SYS_EN to be toggled to restart the part.
Overcurrent Protection (LDO1 and LDO2)
To thermally protect the pass device during a short circuit event, a comparator monitoring the feedback voltage is incorporated. If the output voltage goes below 70% of nominal (typ), the LDO will latch off. This is an independent operation, meaning, a short circuit on one LDO does not affect the operation of the other, nor does it affect the SMPS or high-side switch. An LDO_EN toggle is required to re-start an LDO if it latched off due to a short circuit event. In addition, the current limit should be chosen such that the output voltage will rise to greater than 70% of the final VOUT within 2.74 ms in order to keep the short-circuit circuit from falsely tripping.
Overcurrent Protection (High-Side Load Switch)
There are two overcurrent protection circuits incorporated; one provides a current limit feature, the other provides a short circuit protection feature. Under normal operation, the current is sensed through a sense resistor connected to ISNS[x]+ and ISNS[x]- and limited by the equation:
I LIMIT(LDO) + V SNS[x] R SNS[x]
(eq. 4)
where, RSNS[x] is the sense resistor for LDO1 and LDO2, and VSNS[x] is the current limit threshold. To calculate RSNS[x], the minimum VSNS[x] value and the maximum operating current should be used.
Supply ISNS [x ]+ ISNS [x] - output LR _ G[x] LR _ FB [x] SCP 70% VREF ILIMIT VREF EA
There are two primary protection features of the internal high-side 2.8 A (typ.) current limit. The first protection involves a short circuit condition during startup, and the second involves an overload condition after startup. During startup, if the output does not exceed 4.5 V (typ.) in 1.5 ms (typ.), the device is considered to be in a "hard" short circuit condition, and is latched off. In addition, if the device does not exceed VIN - 3.75 V (typ.) in 3 ms (typ), the device is considered to be in a "soft" short circuit condition, and is latched off. Furthermore, if VHS_S goes below VIN - 3.75 V (typ), during normal operation, for more than 3 ms (typ), the device is considered to be in a "soft" short circuit condition, and is latched off. Once the high-side switch has been latched off, a HS_EN toggle will be required to reset it.
Overvoltage Clamp (High-Side Load Switch)
The source output of the high-side switch is clamped during a high battery condition. This protects any load connected to the source from seeing a double battery or load dump condition. If the input rises above 16 V (typ), the internal gate of the high-side switch will be pulled low to keep the source from rising. The high-side switch will operate in this linear mode until the input voltage exceeds 18.5 V (typ) at which point the entire IC will shutdown.
Figure 21.
APPLICATION INFORMATION
Setting the Output Voltage LDO1 and LDO2 Pass Device Selection
To set the output voltage of any of the controllers or regulators, use the following equation:
V OUT[x] + V REF 1 ) R1 R2
(eq. 5)
where, R1 is the resistor that is connected from VOUT[x] to the feedback pin of its respective channel and R2 is connected from that feedback pin to ground. To reduce the effect of input offset current error, it is customary to calculate R1 with R2 equal to 1 kW.
The LDO controllers have been optimized to give the best performance with the NTD20P06L p-channel MOSFET. While other p-channel MOSFET can be used, specifications in the electrical table are guaranteed only with the NTD20P06L, and using a different MOSFET may require external compensation to stabilize the output. The NTD20P06L can be used as the pass device for both controllers, and is rated with a -60 V max VDS. This device comes in two different packages allowing great flexibility
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NCV8855
when designing the thermal solution. The IPAK package can be attached to the radio's metal enclosure or it can be attached to an independent heatsink. If output current demands are low, then a DPAK package can be used for a surface mount solution.
LDO Output Capacitor Selection
The LDO controllers have been optimize and compensated to work with a variety of output capacitors. Aluminum electrolytic capacitors with an ESR up to 5 W to ceramic capacitors with an ESR down to 10 mW can be used. Depending on load requirements, the output capacitor can range from 10 mF to as much as 100 mF. There are many capacitor vendors which supply automotive rated parts that fall within these ranges. For example, the Nichicon UD or PM type capacitors are suited well for the LDO controllers and automotive radio application. Values outside of these ranges can be used, but may require external compensation.
SMPS1 MOSFET Selection
For the DRV_VPP supply, a local bypass capacitor is not only required for stability, but also to reduce noise and supply peak currents during operation. Use a 1 to 4.7 mF, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size. This capacitor must be referenced to PGND. The bootstrap circuit comprises a charge storage capacitor (CBST1) and the internal bootstrap diode. Typical CBST1 values range from 100 nF to 1 mF. The average forward current can be estimated by the following equation:
I BST1 + Q GATE FSW
(eq. 6)
where, QGATE is the total gate charge. The average forward current through the internal diode should not exceed its rated maximum of 12 mA. This puts a limitation on the MOSFETs used at a particular switching frequency. The power dissipation for the internal MOSFET drivers can be calculated using the following equation:
Pd SMPS1_drv + Pd GH1_drv ) Pd GL1_drv Pd GH1_drv + Q GH1 Pd GL1_drv + C GL1 V GH1 V GL1
2
(eq. 7) (eq. 8) (eq. 9)
SMPS1 has integrated MOSFET drivers optimized for driving N-channel MOSFETs in a synchronous buck configuration. The lower MOSFET driver is designed to drive a ground-referenced low RDS(on) n-channel MOSFET. The supply rail for the lower driver is internally connected to DRV_VPP and the PGND pin is it's ground reference. The upper MOSFET driver is a floating gate driver designed to drive low RDS(on) n-channel MOSFETs. A bootstrap circuit referenced to SN1 as shown in figure 1 develops the supply rail for the upper MOSFET driver. The driver circuitry includes non-overlap protection. The non-overlap protection prevents both Q1 (upper MOSFET) and Q2 (lower MOSFET) from being on at the same time, and minimizes the associated off times. This helps reduce power losses in the switching elements. The non-overlap protection circuit accomplishes this by controlling the delay from Q1's turn-off to Q2's turn-on, and from Q2's turn-off to Q1's turn on by monitoring the voltage at the SN1 and GL1 pins. When the internal PWM signal goes low, GH1 will go low, turning Q1 off. However, before Q2 can turn on, the non-overlap protection circuit waits for the voltage at the SN1 pin to fall below 1.8 V. Once SN1 falls below the 1.8 V threshold, GL1 will go high, turning Q2 on. However, if SN1 does not fall below 1 V in 100 ns, the safety timer circuit will override the normal control scheme and drive GL1 high. This will help insure that if Q1 fails to turn off it will not produce an over-voltage at the output. Similarly, to prevent cross conduction during Q2's turn-off and Q1's turn-on, the non-overlap circuit monitors the voltage at the gate of Q2 through the GL1 pin. When the internal PWM signal goes high, GL1 will go low turning Q2 off. However, before Q1 can turn on, the non-overlap protection circuit waits for the voltage at GL1 to drop below 2 V. Once this has occurred, GH1 will go high, turning Q1 on.
FSW FSW
where, QGH1 is the total gate charge of the upper MOSFET, CGL1 is the total input capacitance of the lower MOSFET, VGH1 = VGL1 = 7.2 V (typ.) which is the DRV_VPP output voltage. One method to improve the IC power dissipation is to diode-or the 8 V SMPS output to the DRV_VPP pin. This will override the internal regulator and the IC will run from the SMPS output. Doing this will incrementally increase the gate drivers power dissipation, but will reduce the loss associated with the DRV_VPP running from battery. For example, if the DRV_VPP is operating at 12 mA from a 14.4 V battery to power SMPS1's gate driver circuit, the power dissipation from this will be 90 mW. In addition, with a 20 nC GH1 change and a 1.8 nF GL1 capacitance, the gate driver loss will be 80 mW. This is a total of 170 mW of power dissipation due to running the gate drivers at 340 kHz. However, if there was a diode-or to the DRV_VPP from the 8 V output of one of the SMPSs, then the DRV_VPP LDO losses are eliminated, and the total power dissipation from running the SMPS1 gate drivers reduce to 95 mW. The improvement gets better when accounting for SMPS2's gate driver loss. This savings can prove to be beneficial in fast FSW and high current applications. There are two recommended n-channel MOSFET for SMPS1, the NTD24N06, which has a 60 V max VDS, and the NTD5407N, which has a 40 V max VDS. Determining which MOSFET to use is predicated by the load dump requirements. The same device can be used for the upper and lower MOSFET. The benefit of this is reduced cost due to economies of scale.
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NCV8855
SMPS2 Diode Selection SMPS Output Capacitor Selection
The diode in SMPS2 provides the inductor current path when the power switch turns off. This is known as the non-synchronous diode or commutation diode. The peak reverse voltage is equal to the maximum operating input voltage. The peak conducting current is determined by the internal current limit. The average current can be calculated from:
I D(avg) + IOUT2 1 * VOUT2 VIN_SW
(eq. 10)
The output capacitor is a basic component for the fast response of the power supply. In fact, during load transient, for first few microseconds they supply the current to the load. The controller recognizes the load transient and proceeds to increase the duty cycle to its maximum. Neglecting the effect of the ESL, the output voltage has a first drop due to the ESR of the bulk capacitor(s).
DVOUT ESR + DIOUT ESR
(eq. 13)
However, the worse case diode average current occurs during a short circuit condition. For a diode to survive an indefinite short circuit condition, the current rating of the diode should be equal to the maximum current limit which is 3.6 A. Thus the MBRS4201T3 is the diode of choice.
Inductor Selection
A lower ESR produces a lower DV during load transient. In addition, a lower ESR produces a lower output voltage ripple. The voltage drop due to the output capacitor discharge can be approximated using the following equation:
DVOUT discharge + 2 COUT (DIOUT) VIN min
2
L D MAX * VOUT (eq. 14)
Both mechanical and electrical considerations influence the selection of an output inductor. From a mechanical perspective, smaller inductor values generally correspond to smaller physical size. Since the inductor is often one of the largest components in SMPS system, a minimum inductor value is particularly important in space-constrained applications. From an electrical perspective, smaller inductor values correspond to faster transient response. The maximum current slew rate through the output inductor for a buck regulator is given by:
Inductor Slew Rate + dI L dt + VL L
(eq. 11)
where, DMAX is the maximum duty cycle value, which is 90%. Although the ESR effect is not in phase with the discharging of the output voltage, DVOUT(ESR) can be added to DVOUT(discharge) to give a rough indication of the maximum DVOUT during a transient condition. Simulation can also help determine the maximum DVOUT; however, it will ultimately have to be verified with the actual load since the ESL effect is dependent on layout and the actual load's di/dt.
SMPS Input Capacitor Selection
Where IL is the inductor current, L is the output inductance, and VL is the voltage drop across the inductor. This equation indicates that larger inductor values limit the regulator's ability to slew current through the output inductor in response to output load transients. Consequently, output capacitors must supply (or store) sufficient charge to maintain regulation while the inductor current "catches up" to the load. This results in larger values of output capacitance to maintain tight output voltage regulation. In contrast, smaller values of inductance increase the regulator's maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. In continuous conduction mode, the peak-to-peak ripple current is calculated using the following equation:
I PP + FSW VOUT L 1* VOUT VBATT
(eq. 12)
The primary consideration for selecting the input capacitor is input RMS current. However, since there are two SMPS running out-of-phase with each other, calculating the input RMS current can be complicated. The graphs below shows how the input RMS current is affected by differing phase angles between SMPS1 and SMPS2. The plot below was generated with VOUT1 at 5 V with a load of 2 A and an output inductor value of 10 mH, and VOUT2 at 8 V with a load of 4 A and an output inductor value of 10 mH.
3.00 2.80 2.60 2.40 2.20 Irms 2.00 1.80 1.60 1.40 1.20 1.00 0.00 60.00 120.00 180.00 240.00 300.00 360.00 Phase (VOUT1 vs VOUT2) 9.00 10.00 11.00 12.00 13.00 14.00 15.00 16.00 17.00 18.00
From this equation it is clear that the ripple current increases as L decreases, emphasizing the trade-off between dynamic response and ripple current. For most applications, the inductor value falls in the range between 2.2 mH and 22 mH. There are many magnetic component vendors providing standard product lines suitable for SMPS1 and SMPS2's requirements. TDK offers the RLF12545-PF series inductors, which are recommended for the automotive radio application.
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Figure 22. Irms vs Phase
NCV8855
3.00 2.80 2.60 2.40 2.20 Irms 2.00 1.80 1.60 1.40 1.20 1.00 0.00% 20.00% 40.00% 60.00% 80.00% 100.00% Clock Duty cycle 9.00 10.00 11.00 12.00 13.00 14.00 15.00 16.00 17.00 18.00 Input current 8 V delayed by 144deg or 2/5T No input current Overlap
5V
Figure 23. Irms vs Phase
Here it is shown that the "sweet spot" phase angle (where the input RMS current is the lowest) happens at the same location (in terms of phase relationship) regardless of input voltage. Thus, once the output voltages are known, a sweet spot can be determined. After determining the sweet spot, the input capacitors can be chosen accordingly to handle the RMS current. The purpose of interleaving the two SMPS is to eliminate any overlapping of there input currents. This will reduce the overall input RMS current. Since the outputs are running at different voltages, they will have different duty cycles, and thus running with 180 phase difference does not necessarily guarantee an optimal input RMS current reduction. The figures below describe, graphically, this point.
40% Duty cycle clock
T
2T
Figure 25.
To achieve this optimization, the SYNC function on the NCV8855 will have to be used with a 40% duty cycle clock. However, when looking at the worst-case input RMS (which occurs at high battery) a 40% duty cycle clock will yield the same input RMS current as a 50% duty cycle clock. Thus, the only true benefit of this optimization occurs when a narrow input voltage range is assured. Therefore, a 50% duty cycle clock is always recommended.
SMPS Compensation
The NCV8855 utilizes voltage mode control. The control loop regulates VOUT by sampling VOUT and controlling the duty cycle. Inherent with all voltage-mode control loops is a compensation network.
V IN
Input current Overlap
L OUT V RAMP 8V delayed by 180deg or 1/2T PWM COMPARATOR DCR ESR C OUT C1 C2 C3 R1 V OUT
5V R2 COMP
R3
FB EA V REF
Figure 26.
50% Duty cycle clock T 2T
Figure 24.
Since the 8 V rail has a wider pulse, with a 50% internal clock duty cycle, there will be some amount of input current overlapping which will produce a less than ideal RMS current. The following figure shows an optimized duty cycle where there is no overlapping.
The compensation network consists in the internal error amplifier and the impedance networks ZIN (R1, R3 and C3) and ZFB (R2, C1 and C2). The compensation network has to provide a closed loop transfer function with the highest 0 dB crossing frequency to have fast response and the highest gain in dc conditions to minimize the load regulation. A stable
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control loop has a gain crossing with -20 dB/decade slope and a phase margin greater than 45.
dB w Z1 + 1 R2 @ C2 w Z2 + 1 R1 ) R3 @ C3 w P1 + 1 C 1@C 2 C 1)C 2 w P2 + 1 R3 @ C3
w 1 L OUT @ C OUT
w LC +
w ESR +
1 ESR @ C OUT
Error Amplifier Compensation Network Modulator Gain Closed Loop Gain
Figure 27.
To reiterate, there are 3 primary goals to compensating. Goal 1 is to have a high a unity gain bandwidth (UGB) that is greater than 1/10 the switching frequency, but less than 1/2 the switching frequency. UGB is also known as the crossover frequency. This is the point where the closed loop
gain = 0 dB or a gain of 1. In the plot above, the UGB is the point where the red line crosses the W axis. Goal 2 is to have the closed loop gain cross 0 dB with a -20 dB/decade slope also known as a -1 slope. Goal 3 is to achieve over 45 of phase margin when the gain crosses 0 dB. These are just goals. Sometimes the crossover frequency is reduced below 1/10 FSW in order to meet goal 3. Conversely, some designs will push the crossover frequency as high as it can (as long as it is below 1/2 FSW) with a reduce phase margin of 30 in order to get a faster transient response. The only two absolutes are that the crossover frequency cannot exceed 1/2 FSW and the phase margin has to be greater than 0 at crossover. However, a SMPS operating towards these absolutes will experience sever ringing before it dampens out. To achieve the above goals, the following guidelines should be adopted. - Place wZ1 at half the resonance of wLC - Place wZ2 at or around wLC - Place wP1 at wESR - Place wP2 at half the switching frequency Performing these calculations will take some amount of iterations and bench testing to verify results. However, ON Semiconductor has developed a tool to speed up the design process tremendously with great ease and accuracy. This tool can be downloaded by following the below link. http://www.onsemi.com/pub/Collateral/COMPCALC.ZIP
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AUTOMOTIVE RADIO SYSTEM BLOCK DIAGRAM EXAMPLE NCV8855 WITH NCV8612
1
AUTO SWITCHOVER
LDO3 VOUT3
VBATT 8V
Oring Diodes & Filter
ASO_RAIL
VIN_S3 VOUT3 VOUT3 FB
20 19 16
8V
Output Filter & FB Network
2
VIN-B
6V
SDARS
Output Filter Output Filter
LDO2 VOUT2
4 3
VIN-H VIN-A
VOUT2
18
3.3Vs
VBATT _MON
MONITORING LOGIC
5 HV_DET BO_DET From external CAN transceiver 6 7 8 HOT_FLG_S 10 IGNIN HV_DET BO_DET EN HOT_FLG
LDO1 VOUT1
VOUT1
17
5Vs
Body CAN
VPP HOT_FLG_S HV_DET BO_DET RST DLY RST DLY
Ignition Filter
INGITOIN BUFFER
11
RESET / DELAY
Ignition
VPP
15 14
Power Amplifier
12
IGNOUT
Main m C
SYS_EN HS_EN LDO_EN HOT_FLG
NCV8612
3.3Vs
5V NCV8855
SYS_EN HS_EN VBATT 5 7 SYS_EN HS_EN LDO_EN
Misc. 5 V Logic Misc. 3.3 V Logic
MAIN
6 8
LDO_EN HOT_FLG VBATT
3.3V
HOT_FLG
27
OCSET BST1 GH1
BST2 VIN_SW
11 10
SMPS1 Power Stage 8V output, 4A ILIMIT
25 24 23
SN2
SMPS1 VOUT1
DVD ROM Drive
SMPS2 VOUT2
8V
SN1
9
SMPS2 Power Stage 5V output, 2A ILIMIT
5V
Headunit CAN
21
GL1
SW_FB2 COMP2
3 2 SYNC
29 30
SW_FB1 COMP1 SYNC
4
USB Connector
VBATT
LDO1 VOUT3
AM/FM Tuner
8.5V
39 1 38
LDO2 VOUT4
ISNS1- LR_G1 LR_FB1
ISNS2- LR_G2 LR_FB2
32 33 34
LDO2 Power Stage 3.3V output, 1A ILIMIT
LDO1 Power Stage 8.5V output, 0.4A ILIMIT
40
ISNS1+
ISNS2+
31
3.3V
Main DSP
VBATT
26
VIN
HIGH-SIDE SWITCH
HS_S
28
Active Antenna
Fan
Figure 28.
NOTE: Not all pins are shown above.
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22
NCV8855
PACKAGE DIMENSIONS
QFN40, 6x6, 0.5P CASE 488AR-01 ISSUE A
D
PIN ONE LOCATION
AB
E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30mm FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e L K MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 6.00 BSC 4.00 4.20 6.00 BSC 4.00 4.20 0.50 BSC 0.30 0.50 0.20 ---
2X
0.15 C
2X
0.15 C 0.10 C
40X
0.08 C
L
40X 10 EXPOSED PAD 11
40X b 0.10 C A B
0.05 C
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EEE EEE EEE
TOP VIEW (A3) SIDE VIEW A1 D2
20 21 1 40 31 30
A C K
SEATING PLANE
SOLDERING FOOTPRINT*
6.30 4.20 0.65
40X
40X
E2
1
4.20 6.30
36X
e BOTTOM VIEW
0.30
40X
0.50 PITCH
DIMENSIONS: MILLIMETERS
36X
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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23
NCV8855/D

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